发明名称 MOS MEMORY
摘要 PURPOSE:To simplify the constitution of a multiplexer and at the same time to reduce the power consumption by using in common the output terminals of two CMOS circuits having a three-state output function respectively. CONSTITUTION:An automatic refresh circuit REF consists of an address counter CONT which produces a refresh address signal and a timer circuit and delivers a switch signal phiref of a multiplexer MPX. A three-state output circuit of the MPX consists of p channel MOSFETs Q86 and Q87, n channel MOSFETs Q88 and Q89 and MOSFETs Q90-93. When the signal phiref is set at a low level, the FETs Q87 and Q88 are turned on to transmit the address signal given from a row address buffer R-ADB to a row decoder R-DCR. While the FETs Q91 and Q92 are turned on when the signal phiref is set at a high level to transmit the address signal given from the counter CONT to the decoder R-DCR.
申请公布号 JPS59188886(A) 申请公布日期 1984.10.26
申请号 JP19830062176 申请日期 1983.04.11
申请人 HITACHI SEISAKUSHO KK 发明人 OOISHI KANJI
分类号 G11C11/403;G11C11/34;(IPC1-7):G11C11/34 主分类号 G11C11/403
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