| 摘要 |
PURPOSE:To contrive to speed up the device by reducing the parasitic series resistance and thus improve the integration degree by unnecessitating the mask for gate formation by a method wherein the gate, source, and drain of an MOSFET are enabled to be finely processed in self-alignment manner with each other. CONSTITUTION:A gate electrode film 3 is partly formed on one surface of a semi-insulation substrate 1 via semiconductor active layer 2. An insulator 4 is deposited over the entire surface of the active layer 2 including this electrode film 3, thus forming an insulator layer thinner than said film 3 on the upper part and side surface of said film 3 and on the exposed part of the active layer 2. Further, the insulator 4 is etched by directional etching of high etching directivity, and accordingly the insulator 4 is left only on the side surface of the film 3. The source 5 and the drain 6 are formed on both the side surfaces of this film 3, respectively. A source electrode 7 and a drain electrode 8 are formed on each of the source 5 and the drain 6, and a passivation film 9 is formed over the whole. Thus, the mask for gate formation is unnecessitated, and the parasitic series resistance is reduced, resulting in the improvement of the integration degree. |
