CLOCK STRETCHING CIRCUITRY

摘要

In a data processing system (10) which includes a central processing unit (22) capable of operating at a higher speed than memory device (20) associated therewith, method and apparatus provide for sensing and correcting errors generated in the memory device, particularly as a result of operation of the memory at speeds approaching design limits wherein errors may be introduced into the data. Specifically, clock stretching circuitry includes circuitry (36) which operate the central processing unit at a preselected clock rate, circuitry (42, 44, 46) which senses for data errors and circuitry (38) which introduces delays in the clocking of the central processing unit only in the presence of indicated data errors. The clock stretching interval permits error correcting circuitry (48) to correct identified bit errors in the data before the central processing unit accesses the data.