发明名称 DATA TRANSMISSION SYSTEM
摘要 PURPOSE:To use only two lines between a master and a slave stations by providing the slave station with a shift register which inputs data consisting of a specific number of bits, sending a clock signals of clocks as many as the stages of the register from the main station to the slave station, shifting the shift register by the number of clocks of the clock signal, and transmitting the data of the specific number of bits to the master station. CONSTITUTION:When the master station 1' and slave station 2' require the data consisting of the specific number of bits, the master station 1' sends the clock signals of the specific number of clocks which serves as a trigger signal through a trigger and clock line, and the slave station 2 receives it and sends the data consisting of the specific number of bits to the master station 1' through a data line 5. When the clock signal of 80% of clocks is sent from the master station 1' to the slave station 2' through the trigger and clock line 6, an MMB7 generates a pulse with pulse width tau at the 1st falling of the input clock signal. The shift register 9 latches the signal consisting of the specific number of bits, i.e. four and the signal is shifted, stage by stage, by eight clocks; and the signals of four bits inputted from input lines 10 and 11 are outputted in series and sent to the master station 1' through a data line 5.
申请公布号 JPS59186451(A) 申请公布日期 1984.10.23
申请号 JP19830061790 申请日期 1983.04.08
申请人 FUJITSU KK 发明人 OONISHI MASARU;YAMAGUCHI NOBUHIDE;INANO SATOSHI
分类号 H04L29/08;H04L13/00;(IPC1-7):H04L13/00 主分类号 H04L29/08
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