| 摘要 |
<p>PURPOSE:To attain the level compensation of a write pulse and to prevent unnecessary current consumption at read by increasing a start signal level to a charge pump circuit by a bootstrap circuit. CONSTITUTION:When a high level read control signal is applied to an EPROM by utilizing a terminal of an FETQ3 outputting a high level write pulse thetaW, the ground is interrupted via a coupling capacitor C1 and no unnecessary DC current flows at read. On the other hand, an FETQ7 and a capacitor C2 forms the bootstrap circuit, a high voltage VPP at write is bootstrapped, a start signal level to the charge pump circuit 1 is increased without giving effect on the capacitor C1 and the level of the write pulse thetaW via the FETQ3 is not decreased. Thus, the level compensation of the wirte pulse is attained and the unnecessary current consumption at read is prevented.</p> |
