SIGNAL PROCESSOR

摘要

PURPOSE:To eliminate a phase shift between different kinds of filtering output by connecting plural unit blocks which each include a delay means for a time- series digital signal and a means for filtering its output into an inverse tree structure. CONSTITUTION:Unit blocks F1-F3 which each consists of a delay means 1 for delaying the time-series digital signal and an arithmetic device for filtering plural digital signals with the different amounts of delay from the means 1 are connected into the inverse tree structure. When F1 and F3 use processors PRC with differentiation characteristics and F2 uses a processor PRC with smoothing characteristics, the differential signal (y) of an input signal (x) is obtained by the PRCF1 and in phase with a signal x' which is delayed specific clocks behind the signal (x). The smoothed signal -x'' of the signal x' is obtained by the PRCF2 and in phase with a signal x'' which is delayed specific clocks behind the signal x'. The secondary differential signal y'' of the signal (x) is obtained by the PRCF3 and in phase with a signal y' delayed by specific clocks behind a signal (y). Therefore, those four kinds of output signals are in phase with one another.