发明名称 SIGNAL PROCESSOR
摘要 PURPOSE:To realize high-speed digital differentiation and smoothing processing through the same constitution by processing two digital signals which are sampled in time series and delayed to have a specific interval of time by addition or subtraction on the basis of an external control signal. CONSTITUTION:A signal xk-n of time k-n outputted from a signal delay device 1 by a clock signal CK is inputted to an exclusive logical arithmetic device 2. A signal J, on the other hand, is inputted to the device 2 to decide on adding or subtracting operation between a signal xk+n of time k+n and the signal kk-n, selecting differentiation or smoothing characteristics. The output of the device 2 and the output of the device 1 are added 3 together and ANDed with a coefficient kn by an AND arithmetic device 4. Adding devices 5-7 operate the linear sum of the output signal of the device 4 by repetitive arithmetic and an adding device 8 adds the signal obtained by multiplying a signal xk corresponding to time k by a coefficient k0 to the output signal from the device 7. Then, the output signal gk of the device 8 is a differential or smoothed filtering output signal.
申请公布号 JPS59185422(A) 申请公布日期 1984.10.22
申请号 JP19830060264 申请日期 1983.04.06
申请人 NIPPON DENKI KK;USUI SHIROU 发明人 AKAI TAKASHI;OKAMOTO KATSUROU;USUI SHIROU
分类号 H03H17/02;G06F7/64 主分类号 H03H17/02
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