| 摘要 |
PURPOSE:To prevent the destruction of stored information and mis-reading of it because of signal delay on a word line and to attain high speed operation by detecting the leading of a signal on the word line so as to operate a spare charging means of a data line through its detected output. CONSTITUTION:A dummy line DW3 having almost the same time constant as that of the word lines W1, W2 is provided newly, a circuit 8 detecting that a voltage at a midpoint (m) is nearly 0V is provided to the midpoint, and its output pulse is taken as the precharge signal phip of data lines D, D'. A driving pulse phix is impressed to the dummy line together with the selected word line at the same time so as to prevent the destruction of information of a memory cell at the midpoint (m). Further, an AND gate 7 detecting that the voltage of the dummy line rises sufficiently is provided to the upper end of the dummy line DW3 so as to form a timing pulse phi3 to start sense-up. Thus, since the sense-up is amplified after a signal of the memory cell and a dummy cell is impressed sufficiently to each data line, no mis-reading occurs thereby attaining high speed memory operation. |
