发明名称 PACKET MULTIPLEXING SYSTEM
摘要 <p>PURPOSE:To attain multiplexing with a small quantity of hardware by supervising an idle state of a multiplexing circuit, outputting a packet transmission element timing selected by the multiplexer, receiving a packet data from a packet data transmitter and transmitting the data to a multiplex line. CONSTITUTION:When a line state detecting circuit 5 detects an end flag representing that no transmission data exists on the multiplex line 3, line idle information is transmitted to a priority selecting circuit 6. The priority selecting circuit 6 selects a packet data transmitter 1 having the highest priority among plural packet data transmitters 1, and an external transmission element timing is given to the packet data transmitter 1 only. The selected packet data transmitter 1 transmits the packet data to the multiplex line 3. When the transmission of the packet data is finished, a line idle state detecting circuit 4 detects the state of idle line again and transmits line idle information to the priority selecting circuit 6.</p>
申请公布号 JPS59183556(A) 申请公布日期 1984.10.18
申请号 JP19830058021 申请日期 1983.04.04
申请人 OKI DENKI KOGYO KK 发明人 INOUE HIROSHI;KUROSAKI TOMOYUKI
分类号 H04L12/56 主分类号 H04L12/56
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