CLOCK FREQUENCY SYNCHRONIZING SYSTEM IN DATA TRANSMISSION SYSTEM USING BUFFER MEMORY

摘要

PURPOSE:To keep the frequency synchronism of clocks in a device by controlling a clock frequency so as to make the sum of changed components of an internal capacity of a buffer memory at transmission side and a component of change of an internal capacity of a buffer memory at reception side zero. CONSTITUTION:The internal capacity of the buffer at transmission side is detected and transmitted to the receiving side. A signal inputted from a data input terminal IN at the receiving side is inputted also to an internal capacity extracting circuit 4, a component of change A of the internal capacity of the buffer memory at he transmission side is obtained and outputted to an adder 8. The component A is added to a component of change B of the internal capacity of the buffer memory 6 at the receiving side outputted from an internal capacity detecting circuit 7 at the adder 8, a difference Z between a write clock frequency fs of the buffer memory at the transmission side and a read clock frequency fR of the buffer memory 6 at the receiving side is outputted to a voltage controlled oscillator to control the read clock frequency so that the difference Z is made zero.