| 摘要 |
PURPOSE:To reduce the capacity of a microprogram memory by using the same microprogram to process a common instruction to both accumulators A and B. CONSTITUTION:A common instruction, e.g., LOADA to both accumulators Acc A and Acc B is fetched to an instruction register 2. As a result, a register designation signal A/B is set at ''1'' with a selection enable signal EN set at ''0'', respectively. Then address information a0-a3 are set at 0000. Thus the output P of an NOR gate 10 is set at ''0'', and the output G3 of an EXOR gate 11 is set at ''0''. Then the address information is set at 0000, and the Acc A of an address ''0'' is selected to store the data given from a memory system 1. When LOADB is fetched to the register 2, the signals A/B and EN are set at ''0'' with the address information set at 0000. Then signals P and G are set at ''1''. Therefore the address information is set at 0001, and the Acc B of an address 1 is selected to store the data given from the memory 1.
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