| 摘要 |
PURPOSE:To attain the circuit suitable for digital processing by changing the phase of a clock signal, and controlling the clock signal so that a complex input signal is sampled in an optimum sample phase. CONSTITUTION:The 1st sampler 1' samples an input signal in a data sample timing. The 2nd sampler 2' samples the input signal in a zero cross detecting timing. An identifier 3' performs code identification of an output of the 1st sampler and outputs + or -1. A differentiating device 4' acting like a change detector detecting the change in data is formed by a -bit delay circuit and a subtractor. A multiplier circuit 5' takes a product between the output of the differentiating device 4' and a signal of the 2nd sampler 2' so as to attain carrier phase locking thereby. |
