发明名称 |
MONITOR SYSTEM FOR OPERATION OF PROCESSOR |
摘要 |
PURPOSE:To improve the defect detecting capacity of a maintenance processor by providing a monitor circuit into a communication bus control to monitor that the communication information is delivered every fixed period from the maintenance processor. CONSTITUTION:An alarm circuit 14 monitors the count defect of time slot in a working mode as well as the defective stack of a DTCHK (time slot holding signal). Furthermore the circuit 14 monitors the time slot allotted to a maintenance processor 2 and delivers an alarm signal 18 to a system switching circuit of the processor 2 when the time slot of the processor 2 is not used for a fixed period or longer. Thus the system switching is performed for the processor 2. The processor 2 reads the state registers of data processors 1-1-1-n or confirms the normal answer to the health checking information. Therefore the time slot allotted to the processor 2 is always used within a fixed period of time as long as the operation of the processor 2 is normal. |
申请公布号 |
JPS59183448(A) |
申请公布日期 |
1984.10.18 |
申请号 |
JP19830057788 |
申请日期 |
1983.04.04 |
申请人 |
NIPPON DENSHIN DENWA KOSHA |
发明人 |
YASHIRO ZENICHI;TONAMI SHIYUUICHI;HONDA TAKASHI |
分类号 |
G06F11/30;G06F11/00;G06F15/16;G06F15/177 |
主分类号 |
G06F11/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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