| 摘要 |
In the case of a semiconductor memory having storage elements which are arranged in rows and columns and are selectable with the aid of an address, the intention is for it to be possible to read or write information row by row or column by column. For this purpose, each storage element (SE) has a storage member, for example a flip-flop, which is connected via a first switching member (T5, T6), for example a selection transistor, to a first terminal (QH, /QH) of the storage element and via a second switching member (T7, T8) to a second terminal (QV, /QV) of the storage element. The first terminals (QH) of the storage elements (SE) are connected row by row in each case to a row-bit line, the second terminals (QV) of the storage elements are connected column by column in each case to a column-bit line. The column-bit lines and the row-bit lines lead in each case to write-read amplifier circuits. The connection of the storage members (SG) to the first or second terminal (QH, QV) of the assigned storage element takes place in dependence on a selection signal and an address, which are fed to a row-decoder circuit or column-decoder circuit, respectively. The row-decoder circuit or column-decoder circuit selects from address and selection signal either a row-word line (WLH) or a column-word line (WLV), via which the selection transistors (T5, T6 and T7, T8, respectively) are controlled in such a way as to make them conductive. As a result, the inputs/outputs (K1, K2) of the storage member (SG) ... either with the first terminals ... Original abstract incomplete. <IMAGE>
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