发明名称 New and improved shifter circuit.
摘要 <p>A new and improved shifter circuit for multiplexing bytes of data into various orders on a finite size bus is disclosed. The improved shifter circuit includes an array of barrel shifter circuits arranged into N groups of M shifter circuits per group wherein each shifter circuit has P data input terminals and P output terminals. The letters N, M and P represent integers. Each of the P output terminals of each of the M shifter circuits in a group are coupled to one another, respectively, so as to form N x P output terminals of the array.</p>
申请公布号 EP0122016(A2) 申请公布日期 1984.10.17
申请号 EP19840301456 申请日期 1984.03.06
申请人 UNISYS CORPORATION 发明人 PHELPS, ANDREW EVERETT;WU, ALLEN TA-MING
分类号 G06F7/00;G06F5/01;G06F7/76;(IPC1-7):06F7/00 主分类号 G06F7/00
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