| 摘要 |
<p>A dynamic random access memory arrangement for storing digital television signal data under control of a system clock signal (CK) and input address signals (AO to A17) associated with the data, comprises a dynamic random access memory (1) having a data input (2) and a data output (3) for the data, and an address input (5) for the input address signals, the dynamic random access memory (1) being controlled by a write enable signal WE, a row address strobe signal RAS and a column address strobe signal CAS, and means (Figure 2) to derive the signals WE, RAS and CAS from the system clock signal CK with respective timings each determined by a leading edge of a pulse of the system clock signal CK and delay devices.</p> |
