| 摘要 |
<p>A plurality of identical processor cells are interconnected to form a data processor for processing digital data signals. Each cell includes an arithmetic processing element (20), e.g. a full adder, having three input terminals (Dl, D2, C) and two arithmetic output terminals (PLUS, CARRY). A plurality of memories (22, 24, 26, 36) connected to the arithmetic processing element (20) are individually controllable to supply selected ones of a plurality of predetermined data signals to the input terminals of the processing element in response to control signals from a controller. The memories includes first, second and third single-bit data registers (22, 24, 26), each selectively controllable to load one of the plurality of predetermined data signals, and a multi-bit memory (36) such as a RAM having an output terminal and selectively addressable storage locations. The memories are connected to the arithmetic processing element (20) and the controller such that both logical and arithmetic operations are performed. The data processor includes n times m cells interconnected in an m by n matrix with interior cells and edge cells. Each interior cell is connected to four neighboring cells and each edge cell is connected to at least two neighboring cells and to a data input/output means which supplies data to some of the edge cells and receives data from some of the edge cells. Each cell includes a data bus (BUS) and signal selection means (MUX) for selectively applying one of a plurality of data signals, including at least the signals from the sum output terminal of the adder (20) and the output terminal of the multi-bit memory (361, to the data bus.</p> |
