| 摘要 |
<p>SUBSTRATE BIAS GENERATOR A substrate bias generator for an integrated circuit, metal-oxide-semiconductor (MOS) random access memory (RAM) is described. The on-chip generator includes two input terminals for receiving first and second trains of periodic pulses. The periodic pulses have the same frequency and are phase synchronized. However, the first train of pulses has a greater duty cycle than the second train of pulses. Amplitude transistions associated with the first and second trains of pulses are capacitively coupled to first and second nodes, respectively. A pair of transistors are coupled to the nodes, one transistor for clamping the first node to ground when the second node receives a positive-going voltage transition, and another transistor for selectively coupling amplitude transitions from the first node to the second node. In operation, both nodes are driven more negative with each successive incoming pulse until they reach about -5 volts for the case in which the amplitude of the incoming pulses is 5 volts. A third transistor closes a current path between the first node and the chip's substrate when the substrate voltage is at least one threshold voltage more positive than the first node voltage. As a result, the substrate voltage is driven to a negative level which is about one threshold voltage more positive than the furthest negative voltage level on the first node.</p> |
