| 摘要 |
<p>A logical circuit which is capable of serving not only as a shift register but also as counter comprises a cascade-connection of flip-flops of the same number as bits required. The flip-flops are each provided in its input part with a logical gate group composed of gates which are opened and closed by a shift signal and a count signal. The logical circuit does not require to provide a flip-flop group in each of a shift register part and a counter part as is needed in a conventional shift register/counter circuit. The logical circuit is capable of performing an independent operation of a shift register, an independent operation of a counter and a compound operation of inputting data in serial for initialization and outputting counted data in serial. With the logical circuit of the present invention, the number of gates used is greatly reduced as compared with the prior art shift register/ counter circuit; accordingly, the circuit of the present invention is of particular utility when formed as a large scale integrated circuit.</p> |
