| 摘要 |
PURPOSE:To reduce the capacity dependability of an operating speed of a gate circuit, and the dependability to fan-out numbers, also to increase the fan-out numbers, and to increase the degree of freedom of a logical design, by using a pnp transistor for an inputting circuit, and adding an off-buffer circuit to an outputting circuit. CONSTITUTION:When one of input signals IN is in a low level, the base of a TR Q7 is reduced, the base of a TR Q9 of an otput stage is set to a low level, and also the base voltage of an off-buffer use TR Q8 is set to a high level. Therefore, an output signal OUT becomes a high level. Also, in case when the input signals IN are all in a high level, the output voltage OUT becomes a low level, and a circuit is operated as an NAND gate. In this circuit, a variation of a switching time tpd against a variation of a load capacity CL is extremely reduced. Its reason is because the capacity dependability of a rise time of the output signal is reduced by an off-buffer circuit of an output stage. Also, a current flowing into an output stage of the prestage from an input side of a gate circuit is reduced by a pnp TR of an input stage, and the maximum fan-out number of each gate circuit is increased.
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