发明名称 INTERMITTENT RECEIVING SYSTEM
摘要 PURPOSE:To save power consumption by turning off a power source of an unnecessary circuit, when a frame synchronization is secured and when a part of a synchronizing word and one-unit length data by which a bit error in data is not detected are received, in a slave station. CONSTITUTION:In a master station, a data output of a frame constitution as shown in a figure (a) is generated. A, B and S denote one frame, one unit length, and a synchronizing word, respectively, and D1-Dn are one-unit length data, and (n) pieces have all the same contents. In a receiving system of a slave station C, the synchronizing word is detected by a detecting circuit 26, it is checked that the synchronizing word is detected correctly by a frame synchronizing circuit 27, and the synchronization is secured. After the synchronization is secured, a power source except that of a circuit required for maintaining the frame synchronization becomes off. In the figure (a), however, in the part of the synchronizing word S and the part of the data D1, the power source is set to on by a power source on and off controlling circuit 30. When a bit error is detected in the data D1, the power source is held in on-state, whether an error exists or not is checked by a bit error detecting circuit 28 with regard to the data D2, and the same processing as that of the data D1 is executed.
申请公布号 JPS59181733(A) 申请公布日期 1984.10.16
申请号 JP19830054533 申请日期 1983.03.30
申请人 NIPPON DENKI KK 发明人 TAMUKI IZUMI
分类号 H04B1/16;H04B7/15;H04B7/155 主分类号 H04B1/16
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