| 摘要 |
PURPOSE:To accelerate and to reduce the power consumption of a semiconductor memory array without increasing a chip area by coupling a main decoder, a plurality of subdecoders and memory cells of blocks corresponding to the subdecoders via selective lines. CONSTITUTION:A memory array M4 has a main decoder MD and a plurality of subdecoders SD1-SDk disposed at the prescribed interval to the decoder MD, and a memory matrixes divided into (K+1) pieces therebetween. The decoder MD and the subdecoders SD1-SDk are coupled by a main decoder selective line MPL2 made of metal such as aluminum, and the subdecoders SD1-SDk and the divided memory cell blocks BL1-BLk are coupled by sub selective lines SPL1- SPLk made of polysilicon. In this manner, the sub selective line can be shortened to obtain high speed, and the number of cells can be reduced by one sub selective line, thereby reducing the power consumption. |
