| 摘要 |
<p>A computer system having a central processing unit (12), a dynamic memory controller (26) an error detection and correction network (16) and a dynamic memory (14) for storing data that are subject to being refreshed and to data bit errors. The dynamic memory controller (26) has a refresh mode for controlling access to the memory only to refresh the data, a refresh with error detection and correction mode, for controlling access to the memory to merge or simultaneous refresh a row of data while detecting and correcting data bit errors, and a read/write mode for controlling access to the memory in response to CPU requests for a read/write memory operation. </p> |
