| 摘要 |
A self-aligned LDMOS device and method and an integrated circuit made thereby which exhibits an inherently by self-aligned channel region allowing for the integration of LDMOS devices having a relatively short channel length (Lf) and hence higher gain than previously described devices. The channel length (Lf) of the device is set by the difference in the coefficient of diffusion between the P-well (16) and source implant (26). The source implant (26) is made through the same oxide window (20) used in forming the P-well (16). The resulting shorter channel length (Lf) provides for the integration of smaller and, therefore, a greater number of even faster devices per given die area. The method of the present invention is fully compatible with standard bipolar processing sequences and eliminates concern over alignment tolerances while simplifying the gate photo step. |
