| 摘要 |
<p>A gate array LSI device having inner gate circuits whose performance is not affected by load capacitance at their output terminals and which have a large fan-out number. The inner gate circuit comprises one or more PNP-type transistors (Q6-1...Q6-m), each of which receives an input signal (IN1 ... INm) atthe basethereof; a first NPN-typetransistor(Q7) whose base is connected to the emitters of the PNP-type transistors; and an output buffer circuit including a second NPN-type transistor (Q9), which is controlled by the emitter current of the first NPN-type transistor and which removes electric charge due to load capacitance from an output terminal, and a third NPN-type transistor (Q.) which is controlled by the collector cu rrent of the first NPN-type transistor and which is connected in series to the second NPN-type transistor so as to supply a charging current to the output terminal.</p> |
