| 摘要 |
PURPOSE:To write data accurately by determining the timing of an address signal in a data write cycle on a prescribed condition. CONSTITUTION:A signal generating circuit 1 provided with delay circuits 12, 13, 14, and 15 which output chip selecting signals CS1' and CS1 obtained by delaying successively a chip selecting signal CS', an address input buffer circuit 2 provided with delay circuits which output address signal A'i and Ai' obtained by delaying successively an address signal Ai in response to the signal CS'1 and an address decoder circuit 3 where plural decoder parts performing the address decoding in response to signals A'i and Ai' are provided and the signal Ai' is given to decoder parts to which only the signal A'i is given are provided. The signal A'i has the level changed between the trailing edge of the signal CS' and the leading edge of the signal CS and after the trailing edge of the signal CS, and the signal A'i' has the level changed after the trailing edge of the signal A'i synchronously with the leading edge of the signal CS. |
