| 摘要 |
PURPOSE:To judge the zero value of plural data in a short time with less quantity of hardware, by judging that, when calculated results of plural data are zero value and no carry is detected, all the plural data are zero value. CONSTITUTION:When all data A-C set in registers 15-17 are zero value, the adding result of a logical adder 10 is zero value and ''1'' is outputted from a zero-value detecting circuit 11. Since no carry is generated in the process of addition of the adder 10, a carry detecting circuit 12 outputs ''0'' and an inverter 13 outputs ''1''. Therefore, when all the data A-C are zero value, ''1'' is outputted from an AND gate 14. Moreover, when any one of the data A-C is not zero value, the output of the adder 10 does not become zero and ''0'' is outputted from the detecting circuit 11. When carry is generated and ''1'' is outputted from the detecting circuit 12 and ''0'' is outputted from the inverter 13 even though a calculated result is zero value, the gate 14 outputs ''0''. Therefore, when ''0'' is outputted from the gate 14, at least one of the data A-C is not zero value. |
