| 摘要 |
PURPOSE:To improve an operating frequency, by reducing the number of field effect transistors used, realizing a simple circuit configuration, and minimizing the area exclusively used by an LSI and signal delay time. CONSTITUTION:For example, out of four pieces (four bits) of circuits 32 for m- stage bit, m-stage input terminals 201 and 202 of the 1st stage (m=1) are respectively connected correspondingly to the output terminals 101 and 102 of a circuit 31 for 1st stage carrying. Out of the circuits 32, mutual connection of each stage of 2<=m<=n uses the logical output of the previous stage as the logical input of next stage. Moreover, by connecting the m-stage output terminals 291 and 291 of the circuit 32 for the final stage (m=n bit) with each other and their connecting point with a carry-out terminal 294 through an inverter 293, this circuit is used as a carrying circuit of all adder circuits of a 4-bit parallel processing system constituted with complementary type MOSs. |
