| 摘要 |
PURPOSE:To read out also data recorded under the state that the bit interval of a data leading part is narrowed without losing reliability by constituting the titled circuit so that the 2nd flying clock having different frequency from the 1st flying clock is generated and providing the titled device with a switching means switching two flying clocks. CONSTITUTION:A flying clock generating circuit 9 generates a clock with frequency fd:(fd=fc+DELTAfc) different from the frequency fc of a flying clock generatting circuit 1. AND gates 8, 10 and an OR gate 11 constitute a switching circuit. Since an input signal 3-12A approximately coincides with the frequency fc of the 1st flying clock generating circuit 1 at the write time, a PLL7 can input data easily. At the read time, an input signal 3-12B can be easily inputted by setting the frequency fd of the 2nd flying clock generating circuit to fc<fd= fc+DELTAfc<fc+DELTAf even if the leading bit of the data is stopped. |
