发明名称 BUFFER MEMORY CONTROLLING SYSTEM
摘要 PURPOSE:To prevent extreme lowering of buffer hit ratio of access from a device of low access frequency by determining a block to be replaced only when memory access request from a device to which replace block determining device is allotted is received. CONSTITUTION:When the device selection signal SEL 0 is logic ''1'', an LRU writing controlling circuit 13-0 attains to operatable state. At the same time, a selection circuit 7-4 selects and outputs a replace level signal from a replace circuit 14-0. When the device selection signal SEL1 is logic ''1'', an LRU writing controlling circuit 13-1 attains to operatable state, and at the same time, the selection circuit 7-4 selects and outputs a replace level signal from a replace circuit 14-1. In the case where a coincidence signal FOUND goes to logical ''0'' for memory access from the central processing unit 2, a replace level signal from the replace circuit 14-0 is outputted as a data selection signal WAY through the selection circuits 7-4 and 7-1.
申请公布号 JPS59177783(A) 申请公布日期 1984.10.08
申请号 JP19830052056 申请日期 1983.03.28
申请人 FUJITSU KK 发明人 TATEISHI TERUTAKA
分类号 G06F12/08;G06F12/12 主分类号 G06F12/08
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