| 摘要 |
PURPOSE:To reduce a bit line load current for all memory cells including a defective memory cell by making clock given to the load between a pair of bit lines and a power source low only when, at least, in non-selection state (stand-by state) and cutting off a current conducting to the load. CONSTITUTION:A pulse generating circuit PG has clock pulse generating circuits PG0, PG1,...PG1-1 PG1 for each low address signals A0, A1,...A1-1 and chip select signal Cs. Accordingly, when any one of A0, A1,...A1-1, signal -CS changes, for instance, signal A0 changes, a clock pulse generating circuit PG0 generates a clock phi through an OR circuit OR. When the signal changes the non-selection state to the selection state or reversely, or when the line of selected memory cell changes, the clock generating circuit PG generates the clock phi. By this circuit, the clock phi that acts as the gate voltage of a load transitor QL is made a low level at least in the non-selection state, and the supply of the current from a power source Vcc to the memory cell is stopped during this while. |
