发明名称 |
VECTOR PROCESSOR |
摘要 |
PURPOSE:To process at a high speed a DO loop including the multiplex condition decision by erasing a vector instruction to be invalidated within an instruction starting circuit in case the vector mask registers have the same value. CONSTITUTION:The vector instructions read out of a main memory 9 are sorted for data processing by a decoder in an instruction control unit 8. The results of this sorting are stored in registers 1-5. These stored vector instructions and the decoding information on the vector mask registers are sent to a vector instruction starting logical circuit 6. The circuit 6 receives the resource idle information sent from plural resources through a bus 15 and the erasing indication for positive and comprementary mask value using instructions detected by a masking data detecting circuit 7 through buses 16 and 17. Then the vector instruction is assigned to each resource through a bus 18 only when the vector instruction start is significant. |
申请公布号 |
JPS59176875(A) |
申请公布日期 |
1984.10.06 |
申请号 |
JP19830050398 |
申请日期 |
1983.03.28 |
申请人 |
HITACHI SEISAKUSHO KK;HITACHI COMPUTER ENGINEERING KK |
发明人 |
YAMADA NAOKI;AOYAMA TOMOO |
分类号 |
G06F17/16;G06F15/78;(IPC1-7):G06F15/347 |
主分类号 |
G06F17/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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