| 摘要 |
PURPOSE:To reduce the power consumption of an A/D converting circuit by using C- MOS integration circuits to constitute 2N units of voltage comparators and a logical circuit which delivers N units of digital codes, etc. with N-bit resolution. CONSTITUTION:An input signal is applied to a terminal 1; while the maximum and minimum reference voltages to receive A/D conversion are impressed to terminals 3 and 2 respectively. Resistances R1-R255 having equal value to each other and resistances R0 and R256 having 1/2 value of R1-R255 are connected in series to those terminals 1-3 in the case of 8-bit resolution for example. The input signal is connected to the positive input of a voltage comparator Ci (i=1-256); while the juncture ni of the resistance is connected to the negative input of the comparator Ci. When input voltage V1>Vi (voltage of juncture ni) is satisfied, the output Qi of the comparator Ci is set at logic ''1''. Then the Qi is set at logic ''0'' with VI<Vi. These logic values are supplied to a code converting circuit R via a 3-input NAND gate Ni, a transfer gate Ti and an inverted amplifier Ii. In this case, only the output of the amplifier Ii is set at logic ''1'', and the outputs of other inverted amplifiers set at logic ''0'' with Vi<VI<Vi-I. These logic values are supplied to the circuit R. The circuit R converts the logic value into a code of 8 bits and delivers it via a holding circuit L1. |
