发明名称 DIGITAL SIGNAL PROCESSOR
摘要 PURPOSE:To shorten the arithmetic time by providing a register which stores the maximum or minimum value in response to the presence or absence of an overflow and a carry between a logical arithmetic circuit and a common signal line. CONSTITUTION:The input data series stored in an RAM2 are supplied to a multiplying circuit 4 via a common signal line BUS under the control of a sequencer SEQ1 and multiplied by the filter coefficient stored in an ROM. The output of multiplication is supplied to a logical arithmetic circuit 5. The circuit 5 adds the output of a temporary memory circuit 6 and the result of multiplication of the circuit 4. Then the result of addition is written to a register REG7 and the circuit 6 when the result of addition has no overflow. If the result of addition has an overflow and also a carry, the negative maximum value is written to the REG7. While the positive maximum value is written to the REG7 when no carry exists with the result of addition. The data is held at the REG7 until the data is read out of the REG7 in case the overflow processing is carried out. Thus the processing is excluded with the software, and therefore the arithmetic time can be shortened.
申请公布号 JPS59176919(A) 申请公布日期 1984.10.06
申请号 JP19830050682 申请日期 1983.03.25
申请人 MATSUSHITA DENKI SANGYO KK 发明人 HONMA KOUICHI;SATOU YOSHIO
分类号 G06F7/38;G06F7/508;G06F17/15;H03H17/02 主分类号 G06F7/38
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