发明名称 SJELVINSTELLANDE REGULATOR
摘要 The regulator has a number of calculating units, and is self-adjusting w.r.t. a number of parameters. It comprises a main shift register (12) connected to the output of the processor (10) and regulates and stores a sequence of dimensions from the system in the form of output signals. A second main shift register (13) connects to the system input, and stores a sequence of other dimensions, comprising system input signals. Both registers register output and input signals respectively at specific times after shifting one position. - A primary calculator (19) calculates a function which expresses the present difference between one of the output signals and one of the corresponding input signals. A further calculator (22,26) directly or indirectly connects to the two shift registers (12,13) and the system (10) input, and brings together the dimensions stored in the registers to form an observation vector.
申请公布号 SE8404988(L) 申请公布日期 1984.10.05
申请号 SE19840004988 申请日期 1984.10.05
申请人 ASEA AB 发明人 CEGRELL T;HEDQVIST T
分类号 G05B13/00;(IPC1-7):G05B13/00 主分类号 G05B13/00
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