| 摘要 |
PURPOSE:To transmit and receive a data and a clock in optional speed with a circuit of comparatively small size by using a ternary signal (0, 1, 2). CONSTITUTION:A data Di at a transmission side 10 is fed to an FF 12 and becomes an NRZ code by a clock Ci. An RZ signal (3) is produced at an AND gate 14 by a Q output (1) and the clock Ci, the output (3) is amplified by a driver 16, a clock Ci(2) is amplified by a driver 18, these outputs a drive a light emitting diode 20 to obtain a ternary level signal of (0, 1, 2). The signal is received by a photodetector 32 at a receiving side 30, amplified at an amplifier 34 and compared with each threshold value at identifying circuits 38 and 40. Then, the clock extraction and data reproduction are attained, the clock is outputted as a C0 via a delay circuit 44 and the data is outputted as a reproduced data D0 from a Q output terminal of a D-FF 42. |
