发明名称 FORMING CIRCUIT OF SYNCHRONIZING PULSE
摘要 PURPOSE:To simplify the constitution by frequency-dividing an oscillation output of a VCO, forming a horizontal synchronizing pulse from the frequency-divided output and further frequency-dividing it to control the VCO by an output as a result of phase comparison with the standard horizontal synchronizing pulse. CONSTITUTION:A clock for non-interlace display from the VCO 61 is applied to a frequency dividing circuit 62, where the clock is frequency-divided into 2fh (standard value), its output is supplied to a decoder 63 and decoded outputs Pj and Pk are extracted. This output is fed to an FF64 and a horizontal synchronizing pulse is led out. This pulse is applied to a T flip-flop 65 and frequency- divided by 2/1, this pulse is supplied to a phase comparison circuit 66, where the phase of the pulse is compared with that of the standard horizontal synchronizing pulse. This compared output is supplied to the VCO 61 through a low pass filter 67 as a control voltage.
申请公布号 JPS59175285(A) 申请公布日期 1984.10.04
申请号 JP19830049769 申请日期 1983.03.25
申请人 SONY KK 发明人 MAEDA SATORU
分类号 H04N5/06 主分类号 H04N5/06
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