| 摘要 |
PURPOSE:To read out an estimated quotient at a high speed by using an RAM having small storage capacity by dividing a quotient estimating table into plural parts and selecting one output out of plural ones from the quotient estimating table by bit strings of the divisor and divident. CONSTITUTION:A bit string consisting of respective upper bits of a divident register 1 and a divisor register 3 is inputted to a logical circuit 40 as a bit string 41. A bit string excluding the lower 2-bit of the bit string 41 is inputted to four quotient estimating tables 4200, 4201, 4210, 4211 as a common address through a line 41a. The 2nd bit from the lowmost bit of the bit string 41 is inputted to comparators 4300, 4301, 4310, 4311 through a line 41b and the lowmost bit is inputted to AND gates 4400, 4401, 4410, 4411. All outputs of the AND gates 4400, 4401, 4410, 4411 are inputted to an OR gate 45 and the output of the OR gate 45 is inputted to an estimated quotient register 5. |
