发明名称 CHANNEL SYNCHRONISM CIRCUIT APPLIED TO MULTICHANNEL SEPARATING DEVICE FOR RECEIVING
摘要 PURPOSE:To stabilize the channel synchronism by executing phase control only when two consecutive violations are detected in the form of a specific pattern among N sets of received symbols. CONSTITUTION:In order to prevent an erroneous phase control from being executed when a channel synchronism circuit 9 is synchronized correctly, the phase control is executed by detecting two consecutive violations in the form of specific pattern among N sets of received symbols. That is, when a signal (u) is not obtained in a counter 21, a flip-flop 23 is not set and no phase change is given to each output signal of a frequency-division circuit 18. In case of the out of synchronism of channel, no pulse appears at an output of an AND circuit 12 and when a signal (t) reaches a low level, since a clock signal (m) cannot passes through an AND circuit 10, the phase of each output signal of the frequency division circuit 18 is parted for one period's share of the clock signal (m) during that time and the channel synchronism is established.
申请公布号 JPS59172871(A) 申请公布日期 1984.09.29
申请号 JP19830045314 申请日期 1983.03.19
申请人 NIPPON DENKI KK 发明人 KOBAYASHI EIICHI
分类号 H04L25/497;H04J3/06;H04L7/04;H04L7/08 主分类号 H04L25/497
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