| 摘要 |
PURPOSE:To prevent color blurring by generating and outputting a write clock pulse from the 1st phase locked loop and generating and outputting a read clock pulse from the 2nd phase locked loop having a slow characteristic not in response to noise. CONSTITUTION:The 1st phase locked loop PLL48 comprising a phase comparator 39, a loop filter 41, a voltage controlled oscillator 42, and a counter 43 responds to noise included in a reproduced horizontal synchronizing signal and an output signal of the oscillator 42 can be in a state not synchronized with the phase of the reproduced horizontal synchronizing signal. Further, an upper cut- off frequency of a filter 44 is set to a low frequency so as to eliminate noise in the reproduced synchronizing signal in the 2nd PLL49 comprising a phase comparator 40, the loop filter 44, a voltage controlled oscillator 45, and a counter 46. Thus, a phase error voltage extracted from the comparator 40 is eliminated for the noise included therein and applied to the oscillator 45, where the oscillating frequency is controlled variably.
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