| 摘要 |
PURPOSE:To cope easily with a case even when a data block length or the number of input times are changed by accumulating the number of times where a bit on the same bit location is in a prescribed state every time a data block is inputted to execute the decision by majority. CONSTITUTION:Every time a serial DATAIN is inputted in a period (t), a timing signal generating circuit 21 generates a timing signal of R/W, LOAD/CNT, and CP0-CP2. An RAM23, a memory address counter 24 and a counter 22 have an estimated maximum capacity and every time the DATAIN is inputted in the unit of bits, the counter 24 is advanced to a count value in response to a data block length to supply an address signal to the RAM23, reads a data from the RAM23 and loads it to the counter 22. Only when the DATAIN is in a specific state, the data is incremented and stored in the same address of the RAM23. The counter 22 adds accumulatingly the state where a bit in the same bit location is in a prescribed state and outputs the accumulated value to a majority decision circuit 25 after the input of final data block. |
