发明名称 FAILURE ASSIGNMENT ERASING CIRCUIT AT RECEIVING SIDE OF DSI DEVICE
摘要 PURPOSE:To erase independently failure assignment control information at the receiving side by the receiving side by storing zero to an address corresponding to an undefined line of an information memory connected to the receiving side and writing zero to an address of an assigned control memory at the detection of zero from the information memory. CONSTITUTION:An assigned information code of a PCM signal transmitted on trunking lines of the line number N (<M) from the transmission side of a channel line number M is inputted to an assigned information decoder 71 of the receiving side. An address counter 100 is advanced by one at each assigned frame of a DSI up to 1-M, and an output of the counter 100 is supplied to the control memory 81 assigned to the receiving side and the information memory 101 connected to the receiving side during the decoding execution time of the decoder 71. In the memory 101, zero is stored in an address corresponding to the circuit where the DSI connection is undefined, and when a comparator 102 discriminates the connected information as zero, a write permission signal is given to the memory 81 and a zero output circuit 103. Simultaneously, zero is written in an address of the memory 81 designated by the counter 100 from the circuit 103 and contents of the address not related to the DSI line connection of the memory 81 are cleared.
申请公布号 JPS59172850(A) 申请公布日期 1984.09.29
申请号 JP19830045313 申请日期 1983.03.19
申请人 NIPPON DENKI KK 发明人 OONUKI KATSUMI
分类号 H04J3/17;H04M11/06 主分类号 H04J3/17
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