发明名称
摘要 PURPOSE:To shorten arithmetic word length by providing different discrete transform arithmetic circuits for multi-frequency signals and conduction test signals. CONSTITUTION:Discrete Fourier transform arithmetic circuit 11 is used only for multi-frequency signals, and discrete Fourier transform arithmetic circuit 12 for conduction test signals. Decision circuit 20 decides upon the presence of signals as to outputs of circuits 11 and 12. In this way, peripheral equipments are provided in common. Here, the arithmetic bit length of circuit 11 can be shortened matching with the relatively-small dynamic range, so that it will output the sum of the squares of a sine-wave component and cosine-wave component. On the other hand, the dynamic range of circuit 12 relatively large and the arithmetic bit length should be long on the square sum system, so that it will output the sum of absolute values of the sine-wave component and cosine-wave component. Consequently, two circuits 11 and 12 become nealy equal in output bit length and circuit 20 can also be constituted with adequate arithmetic bit length.
申请公布号 JPS5939955(B2) 申请公布日期 1984.09.27
申请号 JP19780150498 申请日期 1978.12.07
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA;OKI DENKI KOGYO KK;NIPPON DENKI KK;HITACHI SEISAKUSHO KK 发明人 FUJII KENSAKU;IWASE YASUMASA;IIDA MASAO;SHIRASAWA SUSUMU;SAKURAI KOJIRO
分类号 H04L27/26;H04Q1/457 主分类号 H04L27/26
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