| 摘要 |
The arrangement for converting the mean frequency of an AC signal into a parallel digital value contains a known integrating arrangement which is however not reset regularly to zero, but whose contents are accumulated in time with a clock signal whose frequency is higher than the highest frequency of the AC signal. The resulting carry signals are subtracted from the AC signal and only this difference is supplied to the integrating arrangement. This thereby provides a continuous display of the mean frequency, where the resolution can be selected to be more or less as high as required. So that a faster formation of the digital value takes place in the event of a sudden significant change in the frequency of the alternating signal, at least one further arrangement of this type is provided, but with a lower number of digits, and the corresponding digits of both arrangements are compared. If a predefined deviation is exceeded, the value in the arrangement with the higher number of digits is used. <IMAGE>
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