发明名称 OUTPUT CIRCUIT
摘要 PURPOSE:To prevent an output voltage from being decreased rapidly even if an output current is increased by providing the 1st-4th transistors (TRs) and connecting both of a collector of the 1st TR and an emitter of the 3rd TR to an output terminal. CONSTITUTION:When a signal of a low level [below (VCC-VBE)] is applied to an input terminal 1, TRsQ1, Q2 are conductive (saturating state) and an output voltage V0 at an output terminal 2 is V0=VCC-VCE(SAT)Q1 and a current is applied to a load connected to an output terminal 2. When a current I0 is increased, the collector-emitter saturated voltage VCE(SAT)Q1 of the TRQ1 is increased and the output voltage V0 is decreased. When the output voltage V0 becomes VCC-VCE(SAT)Q2-VBE or below, an npn TRQ3, however, starts being conducted, where VCE(SAT)Q2 is a collector-emitter saturated voltage of the TRQ2. Thus, the output voltage is kept to a certain constant voltage even if the output current is increased.
申请公布号 JPS59171317(A) 申请公布日期 1984.09.27
申请号 JP19830046240 申请日期 1983.03.18
申请人 MATSUSHITA DENKI SANGYO KK 发明人 OOTA YUTAKA;MIZUGUCHI HIROSHI;YANO SHIGERU
分类号 H03K17/60;H03K17/0814 主分类号 H03K17/60
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