Semiconductor memory device.

摘要

A semiconductor memory device has memory cells with MIS transistors (Tr1 to Tr4) formed in zones defined by field insulation (FL), each with source (S) and drain (D) regions and a channel region the maximum possible width (Wf) of which is defined by the field insulation (FL). Some of the transistors (e.g. Tr2, Tr3, Tr4) have doped regions (P1, P2, P3), doped with impurity opposite to the conductivity type of the source and drain regions giving them effective channel widths (W2 for Tr2; W3 for Tr3) less than the maximum possible. This lesser width may be zero (Tr4). Multi-level information (e.g. base 3 or base 4) can be stored by setting different channel widths corresponding to its different levels. <<Half-fabricated>> devices, taken to a production stage immediately prior to formation of the doped regions (P1, P2, P3) can be stocked by a manufacturer so that, in response to a customer's order, he need only write in selected information by implanting the doped regions.