Signal decoder for converting a co-directional 64 kbit/s interface signal into a binary information signal, a 64 KHZ clock and an 8 KHZ clock

摘要

A signal decoder converts a co-directional 64 kbit/s interface signal which is divided into half waves into a binary information signal, a 64 kHz clock and an 8 kHz clock. A circuit arrangement is provided for each half wave in which criteria of the signal to be decoded are input into three memories at points in time specified by a counter. The conditions at the outputs of the corresponding memories of each arrangement are combined with OR gates. The decoded signals can be tapped at the outputs of the OR gates. The signal decoder may be employed in the data signal inputs of a system PCM 30F, a PCM exchanger or a 64 kbit/s terminal.