发明名称 FLIP-FLOP CIRCUIT
摘要 PURPOSE:To obtain an FF circuit having a simple constitution and high-speed working by using the 1st-4th logical gate circuits having plural output transistors of open collector constitutions. CONSTITUTION:This FF circuit consists of the 1st-4th logical gate circuits G1- G4. An input data signal -D, a clock signal CK and a set signal -S are supplied to the input of the circuit G1; a data signal -D, a set signal -S and the output signal of one side of the circuit G4 are supplied to the input of the circuit G2; a set signal -S, a clock signal -CK having the phase opposite to the signal CK and the output signal of the circuit G4 are supplied to the input of the circuit G3; and a reset signal -R and the output of one side of each of circuits G1-G3 are supplied to the input of the circuit G4 in the form of a wired AND constitution. Then an output signal Q' is obtained from the output terminal of the other side of the circuit G4, and an output signal Q is obtained from the output of a wired AND constitution of each of circuits G1-G3 respectively. Thus it is possible to obtain an FF circuit having a simplified constitution and high-speed working.
申请公布号 JPS59169221(A) 申请公布日期 1984.09.25
申请号 JP19830042198 申请日期 1983.03.16
申请人 HITACHI SEISAKUSHO KK 发明人 ISHII SHIYUUICHI;USAMI MITSUO
分类号 H03K3/037;(IPC1-7):H03K3/037 主分类号 H03K3/037
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