发明名称 DATA TRANSMISSION SYSTEM
摘要 PURPOSE:To enhance the transmission speed by performing the A/D converting operation of a terminal processing device LCU periodically independently of the calling timing due to a central controller CCU to write digital data in a register and reading out this data at the calling timing. CONSTITUTION:In each of terminal processing devices 30-32, a received signal RXD inputted from a transmission line 20 is supplied to a synchronizing circuit 102 and is synchronized with clocks from a clock generator 107, and a clock which is synchronized in the start-stop system with clock components of the received signal RXD is given to a control circuit 101, and then, the control circuit 101 generates a control signal to read a data part of the received signal into a shift register 104 serially. Meanwhile, the address assigned to a pertinent terminal processing device is preliminarily given to an address comparing circuit 103, and this address and data read into a prescribed bit position of the shift register 104 are compared with each other by an address comparing circuit 103; and if they coincide with each other, data in the shift register 104 is transferred to an I/O buffer 105 and is given to an external device.
申请公布号 JPS59167151(A) 申请公布日期 1984.09.20
申请号 JP19830040581 申请日期 1983.03.14
申请人 HITACHI SEISAKUSHO KK 发明人 HAMANO FUMIO;OBO SHIGERU;HIRAYAMA TAKESHI
分类号 H04Q9/00;H04Q9/14 主分类号 H04Q9/00
代理机构 代理人
主权项
地址