| 摘要 |
PURPOSE:To detect an overrun even in an abnormal state by providing a circuit which resets an overrun latch means according to whether tag-in synchronization is completed or not and a circuit which sets the overrun latch means. CONSTITUTION:When a tag-in signal turns off after the tag-in signal is synchronized, an AND gate 10 meets requirements after the pulse width compensation of a corresponding tag-out signal and an FF17 is reset to turn off the tag- out signal. The AND condition is not satisfied unless the tag-in signal is synchronized, and the conditions is satisfied at the timing wherein the next timing signal turns on and turns off without the response of the corresponding tag-out signal; and the FF17 is reset and an FF18 is set, outputting an overrun signal of a channel. Consequently, the hung-up state of an IO interface is prevented and an data error is prevented even in case of an overrun.
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